Modification and Evaluation of Software-Based Communications Unit of a LSC on Chip

We have evolved several types of Loop Structured Computers (LSCs) to build a system with small hardware overhead to apply it system-on-chip (SoC). In recent studies, we investigated control flow methods with software-based approach with a general-purpose instruction set. In this paper, we proposed two specialized instruction sets for communications in order to reduce transmission latency. One used similar CPU design to the previous study. The other required support of hardware pointers and counters. We evaluated performance of the new systems with simulations with clock cycle level of the CPU. The former instruction set shortened minimum packet transmission latency only a few percent under low traffic, and improved throughput about 10 %. The latter declined minimum packet transmission latency about 20% in number of clock cycles, and increased throughput 30 %. Furthermore, size of communications program was shrieked about 30 %.